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LMH0030_0608 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LMH0030_0608 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 29 page DC Electrical Characteristics (Continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units I DD (3.3V) Power Supply Current, 3.3V Supply, Total V CLK = 74.25 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDIO,VDDSD 66 90 mA I DD (2.5V) Power Supply Current, 2.5V Supply, Total V CLK = 27 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDD,VDDZ, V DDPLL 66 85 mA I DD (2.5V) Power Supply Current, 2.5V Supply, Total V CLK = 74.25 MHz, NTSC color Bar Pattern, Test Circuit, Test Loads Shall Apply V DDD,VDDZ, V DDPLL 85 110 mA AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units f VCLK Parallel Video Clock Frequency V CLK 27 74.25 MHz DC V Video Clock Duty Cycle V CLK 45 50 55 % f ACLK Ancillary Clock Frequency A CLK V CLK MHz DC A Ancillary Clock Duty Cycle A CLK 45 50 55 % t r,tf Input Clock and Data Rise Time, Fall Time 10%–90% V CLK,ACLK,DVN, AD N 1.0 1.5 3.0 ns BR SDO Serial Data Rate (Notes 5, 6) SDO, SDO 270 1,485 M bps t r,tf Rise Time, Fall Time 20%–80%, (Note 6) SDO, SDO 270 ps t r,tf Rise Time, Fall Time 20%–80%, (Note 5) SDO, SDO 500 ps Output Overshoot (Note 4) SDO, SDO 5% t j Serial Output Jitter, Intrinsic 270 M bps, (Notes 5, 9, 10, 11) SDO, SDO 270 350 ps P-P t j Serial Output Jitter, Intrinsic 1,485 M bps, (Notes 6, 9, 10, 11) SDO, SDO 85 125 ps P-P t LOCK Lock Time (Notes 5, 7) (SD Rates) 15 ms t LOCK Lock Time (Notes 6, 7) (HD Rates) 15 ms t S Setup Time, Video Data Timing Diagram, (Note 4) DV N to VCLK 1.5 2.0 ns t H Hold Time, Video Data Timing Diagram, (Note 4) V CLK to DVN 1.5 2.0 ns t S Setup Time, Anc. Data Port Timing Diagram, (Note 4) AD N to ACLK 1.5 2.0 ns t H Hold Time, Anc. Data Port Timing Diagram, (Note 4) A CLK to ADN 1.5 2.0 ns Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VSS =0V. Note 3: Typical values are stated for VDDIO =VDDSD = +3.3V, VDDD =VDDPLL = +2.5V and TA = +25˚C. Note 4: Specification is guaranteed by design. Note 5: RL =75Ω, AC-coupled @ 270 Mbps,RREFLVL = RREFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit. Note 6: RL =75Ω, AC-coupled @ 1,485 Mbps,RREFLVL = RREFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit. Note 7: Measured from rising-edge of first DVCLK cycle until Lock Detect output goes high (true). Lock time includes format detection time plus PLL lock time. www.national.com 6 |
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