PRELIMINARY
CY2SSTU877
Document #: 38-07575 Rev. *E
Page 2 of 9
Pin Description
Pin No.
Name
Description
G1
AGND
Ground for 1.8V analog supply
H1
AVDD
1.8V analog supply
E1, F1
CLK_INT, CLK_INC Differential clock input with a (10K–100K
Ω) pull-down resistor
E6, F6
FB_INT, FB_INC
Feedback differential clock input
H6, G6
FB_OUTT,
FB_OUTC
Feedback differential clock output
B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4,
J5
GND
Ground
F5
OE
Output enable (ASYNC) for CLKT[0:9] and CLKC [0:9]
D5
OS
Output Select (Tied to GND or VDDQ)
D2, D3, D4, E2, E5, F2, G2, G3, G4, G5
VDDQ
1.8V supply
A2, A1, D1, J1, K3, A5, A6, D6, J6, K4,
CLKT [0:9]
Buffered output of input clock, CLK
A3, B1, C1, K1, K2, A4, B6, C6, K6, K5
CLKC [0:9]
Buffered output of input clock, CLK
Table 1. Function Table
Inputs
Outputs
PLL
AVDD
OE
OS
CLK_INT CLK_INC
CLKT
CLKC
FB_OUTT FB_OUTC
GND
H
X
L
H
L
H
L
H
Bypassed/Off
GND
H
X
H
L
H
L
H
L
Bypassed/Off
GND
L
H
L
H
Lz
Lz
L
H
Bypassed/Off
GND
L
L
H
L
Lz,CLKT7
Active
Lz,CLKC7
Active
H
L
Bypassed/Off
VDD
L
H
L
H
Lz
Lz
L
H
On
VDD
L
L
H
L
Lz,CLKT7
Active
Lz,CLKC7
Active
HL
On
VDD
H
X
L
H
L
H
L
H
On
VDD
H
X
H
L
H
L
H
L
On
VDD
X
X
L
L
Lz
Lz
Lz
Lz
Off
X
X
X
H
H
Reserved
Recommended Operating Conditions
Parameter
Description
Condition
Min.
Max.
Unit
TA (Com.)
Ambient Operating Temp
0
70
°C
VDD, AVDD
Operating Voltage
1.7
1.9
V
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