CY2SSTV857-32
Document #: 38-07557 Rev. *E
Page 3 of 9
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV857-32 will
likely be in a nested clock tree application. For these applica-
tions, the CY2SSTV857-32 offers a differential clock input pair
as a PLL reference. The CY2SSTV857-32 then can lock onto
the reference and translate with near zero delay to low-skew
outputs. For normal operation, the external feedback input,
FBIN, is connected to the feedback output, FBOUT. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-32 allows
the user to implement power management schemes into the
design. Outputs are three-stated/disabled when PD# is
asserted LOW (see Table 1).
Table 1. Function Table
Inputs
Outputs
PLL
AVDD
PD#
CLK
CLK#
Y
Y#
FBOUT
FBOUT#
GND
H
L
H
L
H
L
H
BYPASSED/OFF
GND
H
H
L
H
L
H
L
BYPASSED/OFF
X
L
L
H
ZZZ
Z
Off
X
L
H
L
ZZZ
Z
OFF
2.6V
H
L
H
L
H
L
H
On
2.6V
H
H
L
H
L
H
L
On
2.6V
H
< 20 MHz
< 20 MHz
Hi-Z
Hi-Z
Hi-Z
HI-Z
Off
CLKIN
t
(phase error)
FBIN
FBOUT
t
sk(o)
Yx
Yx
Yx
t
sk(o)
Figure 1. Phase Error and Skew Waveforms
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