Differential Clock Buffer/Driver
CY2SSTV855
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07459 Rev. *F
Revised January 2, 2006
Features
• Phase-locked loop (PLL) clock distribution for Double
Data Rate Synchronous DRAM applications
• 1:5 differential outputs
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• SSCG: Spread Aware™ for electromagnetic
interference (EMI) reduction
• 28-pin TSSOP package
• Conforms to JEDEC DDR specifications
Functional Description
The CY2SSTV855 is a high-performance, very-low-skew,
very-low-jitter zero-delay buffer that distributes a differential
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of
clock outputs and one differential pair of feedback clock
outputs. In support of low power requirements, when
power-down is HIGH, the outputs switch in phase and
frequency with the input clock. When power-down is LOW, all
outputs are disabled to a high-impedance state and the PLL is
shut down.
The device supports a low-frequency power-down mode.
When the input is < 20 MHz, the PLL is disabled and the
outputs are put in the Hi-Z state. When the input frequency is
> 20 MHz, the PLL and outputs are enabled.
When AVDD is tied to ground, the PLL is turned off and
bypassed with the input reference clock gated to the outputs.
The Cypress CY2SSTV855 is Spread Aware and supports
tracking of Spread Spectrum clock inputs to reduce EMI
Block Diagram
Pin Configuration
28-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
YT3
VDDQ
FBOUTT
YT2
YC2
GND
VDDQ
FBOUTC
YC3
VDDQ
PWRDWN
FBINT
FBINC
GND
YT0
VDDQ
AGND
YT1
YC1
GND
VDDQ
AVDD
YC0
VDDQ
GND
CLKINT
CLKINC
FBOUTT
FBOUTC
YT0
YC0
YC3
YT3
PLL
PWRDWN
YC2
YT2
YT1
YC1
Powerdown
and test
logic
AVDD
CLKINT
CLKINC
FBINT
FBINC
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