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PRELIMINARY
High-frequency Programmable PECL Clock Generation Module
CY2XP306
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07725 Rev. *A
Revised April 8, 2005
Features
• 60 ps typical Cycle-to-Cycle Jitter
• 30 ps typical Output-Output Skew
• Phase-locked loop (PLL) multiplier select
• LVTTL or XO Input; Six LVPECL Outputs
• Selectable Output Divider (/2)
• 1–133 MHz Input Frequency Range
• 62.5–500 MHz Output Frequency Range
• 36-pin VFBGA, 6 × 8 × 1 mm
• 3.3V operation
• Serially Configurable Multiply Ratios
Block Diagram
QA1
QA1#
QA2
QA2#
QA3
QA3#
QB1
QB1#
QB2
QB2#
QB3
QB3#
/1
/2
0
1
0
1
MR
XTAL
OSCILLATOR
PLL
xM
XIN/REF
XOUT
SER CLK
SER DATA
PLL_MULT
FSELA
FSELB
Pin Configuration (Top View)
6
5
4
3
2
1
ABC
D
E
FG
H
C Y 2X P 306 36 V F B G A P IN C O N F IG U R A T IO N
T O P V IE W
QA 1
VD D A
GN D
XO U T
XIN
VD D B
QA 1 #
GN D
SER _
DA T A
SE R _
CL K
GND
VD D B
QA 2
QB 2
QB 2 #
GN D
QA 2 #
P LL_
MU L T
QA 3
MR
QA 3 #
QB 3
QB 3 #
FSE L A
QB 1
GN D
VD D B
VD D B
GND
FS EL B
QB 1 #
VD D A
VD D A
NC
VD D A
VD D A
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