PRELIMINARY
CY2XP306
Document #: 38-07725 Rev. *A
Page 3 of 9
Two-Wire Serial Interface
Introduction
The CY2XP306 has a two-wire serial interface designed for
data transfer operations, and is used for programming the P
and Q values for frequency generation. Sclk is the serial clock
line controlled by the master device. Sdata is a serial bidirec-
tional data line. The CY2XP306 is a slave device and can
either read or write information on the dataline upon request
from the master device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled high by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the Sdata from HIGH to LOW while the Sclk is at
HIGH. Similarly, stop (P) is defined as switching the Sdata from
LOW to HIGH while holding the Sclk HIGH. Between these two
signals, data on Sdata is synchronous with the clock on the Sclk.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the Sdata LOW before the Sclk rising edge and hold it
LOW until the Sclk falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is one byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2XP306. Two dummy bytes must be transferred before
the first data byte. The CY2XP306 has only three bytes of
latches to store information, and the third byte of data is
reserved. Extra data will be ignored.
Figure 1. Device Connections
Figure 2. Serial Interface Specifications
Figure 3. CY2XP306 Transfer Format
S clk
S data
Sclk_C
S clk_in
S data_C
S data_in
M a ste r D e vice
R p
S clk_in
S data_C
S data_in
S lave D evice
V DD
R p
Start (S)
Stop (P)
Sclk
Sdata
valid data
Acknowledge
Ack
1 bit
8 bits
Data 1
P
Slave Address
Ack
S
Dummy Byte 0
R/W
Dummy Byte 1
Ack
1 bit
1 bit
Ack
1 bit
7 bits
8 bits
1 bit
Data 0
Ack
1 bit
8 bits
1 bit
8 bits