RoboClock
CY7B993V
CY7B994V
Document #: 38-07127 Rev. *F
Page 8 of 15
Absolute Maximum Conditions[5]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–40
°C to + 125°C
Ambient Temperature with
Power Applied............................................–40
°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Input Voltage....................................–0.3V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 40 mA
Static Discharge Voltage........................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................. > ± 200 mA
Operating Range
Range
Ambient Temperature
VCC
Commercial
0
°C to +70°C
3.3V
± 10%
Industrial
–40
°C to +85°C
3.3V
± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min., IOH = –30 mA
2.4
–V
LOCK
IOH = –2 mA, VCC = Min.
2.4
–
V
VOL
LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min., IOL= 30 mA
–
0.5
V
LOCK
IOL= 2 mA, VCC = Min.
–
0.5
V
IOZ
High-impedance State Leakage Current
–100
100
µA
LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])
VIH
LVTTL Input HIGH
FBK[A:B]±, REF[A:B]±
Min. < VCC < Max.
2.0
VCC + 0.3
V
REFSEL, FBSEL, FBDIS,
DIS[1:4]
2.0
VCC + 0.3
V
VIL
LVTTL Input LOW
FBK[A:B]±, REF[A:B]±
Min. < VCC < Max.
–0.3
0.8
V
REFSEL, FBSEL, FBDIS, DIS[1:4]
–0.3
0.8
V
II
LVTTL VIN >VCC
FBK[A:B]±, REF[A:B]±
VCC = GND, VIN = 3.63V
–
100
µA
IlH
LVTTL Input HIGH
Current
FBK[A:B]±, REF[A:B]±
VCC = Max., VIN = VCC
–
500
µA
REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC
–
500
µA
IlL
LVTTL Input LOW
Current
FBK[A:B]±, REF[A:B]±
VCC = Max., VIN = GND
–500
–
µA
REFSEL, FBSEL, FBDIS, DIS[1:4]
–500
–
µA
Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))
VIHH
Three-level Input HIGH[6]
Min. < VCC < Max.
0.87*VCC
–V
VIMM
Three-level Input MID[6]
Min. < VCC < Max.
0.47*VCC 0.53*VCC
V
VILL
Three-level Input LOW[6]
Min. < VCC < Max.
–
0.13*VCC
V
IIHH
Three-level Input
HIGH Current
Three-level input pins excl. FBF0 VIN = VCC
–
200
µA
FBF0
–
400
µA
IIMM
Three-level Input
MID Current
Three-level input pins excl. FBF0 VIN = VCC/2
–50
50
µA
FBF0
–100
100
µA
IILL
Three-level Input
LOW Current
Three-level input pins excl. FBF0 VIN = GND
–200
–
µA
FBF0
–400
–
µA
LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)
VDIFF
Input Differential Voltage
400
VCC
mV
VIHHP
Highest Input HIGH Voltage
1.0
VCC
V
VILLP
Lowest Input LOW Voltage
GND
VCC – 0.4
V
VCOM
Common Mode Range (crossing voltage)
0.8
VCC
V
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
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