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CY7B951-SXI Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7B951-SXI
Description  Local Area Network ATM Transceiver
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B951-SXI Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY7B951
Document Number: 38-02010 Rev. *A
Page 4 of 10
Carrier Detect (CD) and Link Fault Indicator (LFI)
Functions
The Link Fault Indicator (LFI) output is a TTL-level output that
indicates the status of the receiver. This output can be used by
an external controller for Loss of Signal (LOS), Loss of Frame
(LOF), or Out of Frame (OOF) indications. LFI is controlled by
the Carrier Detect input, the internal Transitions Detector, and
the PLL Out of Lock (OOL) circuitry.
The CD input may be driven by external circuitry that is
monitoring the incoming data stream. Optical modules have
CD outputs that indicate the presence of light on the optical
fiber and some copper based systems use external threshold
detection circuitry to monitor the incoming data stream. The
CD input is a 100K PECL compatible signal that should be held
HIGH when the incoming data stream is valid. When CD is
pulled to a PECL LOW (<2.5V Max.), the LFI output will
transition LOW and the Receiver PLL will align itself with the
REFCLK
⋅8 frequency and the recovered data outputs (RSER)
will remain LOW regardless of the signal level on the Receive
data stream inputs (RIN).
In addition, the CY7B951 has a built-in transitions detector that
also checks the quality of the incoming data stream. The
absence of data transition can be caused by a broken trans-
mission media, a broken transmitter, or a problem with the
transmit or receive media coupling. The CY7B951 will detect
a quiet link by counting the number of bit times that have
passed without a data transition. A bit time is defined as the
period of RCLK±. When 512 bit times have passed without a
data transition on RIN±, LFI will transition LOW. The receiver
will assume that the serial data stream is invalid and, instead
of allowing the RCLK± frequency to wander in the absence of
data, the PLL will lock to the REFCLK*8 frequency. This will
ensure that RCLK± is as close to the correct link operating
frequency as the REFCLK accuracy. LFI will be driven HIGH
again and the receiver will recover clock and data from the
incoming data stream when the transition detection circuitry
determines that at least 64 transitions have been detected
within 512 bit-times.
The Transition Detector can be turned off by pulling the CD
input to a TTL LOW (<0.8V). When CD is pulled to a TTL LOW
the LFI will only be driven LOW if the incoming data stream
frequency is not within 1000 ppm of the REFCLKX8 frequency.
LFI LOW in this case will only indicate that the Receiver PLL
is Out of Lock (OOL). When this pin is left unconnected, an
internal pull-down resistor will pull this input to Ground.
Loopback Testing
The TTL level LOOP pin is used to perform loopback testing.
When LOOP is asserted (held LOW) the Transmitter serial
input (TSER±) is used by the Receiver PLL for clock and data
recovery. This allows in-system testing to be performed on the
entire device except for the differential Transmit drivers
(TOUT±) and the differential Receiver inputs (RIN±). For
example, an ATM controller can present ATM cells to the input
of the ATM cell processor and check to see that these same
cells are received. When the LOOP input is deasserted (held
HIGH the Receive PLL is once again connected to the
Receiver serial inputs (RIN±).
The LOOP feature can also be used in applications where
clock and data recovery are to be performed from either of two
data streams. In these systems the LOOP pin is used to select
whether the TSER± or the RIN± inputs are used by the
Receive PLL for clock and data recovery.
Power Down Modes
There are several power down features on the CY7B951. Any
of the differential output drivers can be powered down by either
tying both outputs to VCC or by simply leaving them uncon-
nected where internal pull-up resistors will force these outputs
to VCC. This will save approximately 4 mA per output pair in
addition to the associated output current. If the TOUT± or
ROUT± outputs are tied to VCC or left unconnected, the
Transmit buffer or Receive buffer path respectively will be
turned off. If the TCLK± outputs are tied to VCC or left uncon-
nected, the entire Transmit PLL will be powered down.
By leaving both the RCLK± and RSER± outputs unconnected
or tied to VCC, the entire Receive PLL is turned off. Even
though the Receive PLL may be turned off, the Link Fault
Indicator (LFI) will still reflect the state of the Carrier Detect
(CD) input. This feature can be used for aggressive power
management.
Applications
The CY7B951 can be used in Local Area Network ATM appli-
cations. The operating frequency of the CY7B951 is centered
around the SONET/SDH STS-1 rate of 51.84 MHz and the
SONET/SDH STS-3/STM-1 rate of 155.52 MHz. This device
can also be used in data mover and Local Area Network (LAN)
applications that operate at these frequencies.
The CY7B951 can provide clock and data recovery as well as
output buffering for physical layer protocol engines such as the
SONET/SDH and ATM processing application shown in
Figure 1 and Figure 2.
Figure 1 shows the CY7B951 in an ATM system that uses the
PMC-Sierra PM5345 SUNI, or the IgT WAC-013, or the
Brooktree BT8222 device. Assuming that PM5345 SUNI is
used, the CY7B951 will recover clock and data from the input
serial data stream and pass it to the PM5345 SUNI. The SUNI
device will perform serial to parallel conversion, SONET/SDH
overhead processing and ATM cell processing and then pass
ATM cells to an ATM packet reassembly engine. On the
Transmit side, a segmentation engine will divide long packets
of data such as Ethernet packets into 53 byte cells and pass
them to the SUNI. The SUNI device will then perform ATM cell
processing, such as header generation, SONET/SDH
overhead processing and parallel to serial conversion. This
serial data will then be passed to the CY7B951 which will
buffer this data stream and pass it along to the transmission
media.
The CY7B951 provides the necessary clock and data recovery
function to the PM5345. These differential PECL clock and
data signals interface directly with the RXD
± and RXC± inputs
of the SUNI device as shown in Figure 2. In addition, the
CY7B951 provides transmit data output buffering for direct
drive of cable transmission media. Lastly, the CY7B951
provides a bit rate reference clock to the SUNI transmitter by
multiplying a local clock by eight allowing an inexpensive
crystal oscillator to be used for the local reference.


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