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CY2SSTV857-32
Document #: 38-07557 Rev. *E
Page 9 of 9
Document History Page
Document Title: CY2SSTV857-32 Differential Clock Buffer/Driver
DDR400/PC3200-Compliant
Document Number: 38-07557
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
128403
08/04/03
RGL
New Data Sheet
*A
129080
09/05/03
RGL
Changed the maximum operating frequency from 200 MHz to 250 MHz
Added Industrial Temperature Range
Changed the power supply from 2.5V to 2.6V
Changed the supply voltage from 2.38, 2.5 and 2.63V to 2.3, 2.6 and 2.7V,
respectively, in the DC Electrical Specifications table
Changed the Fo value from 170 MHz to 200 MHz in the DC Electrical Speci-
fications table
Changed the Duty Cycle from 49.5 and 50.5 to 49 and 51% (60 to 170 MHz)
Changed the Duty Cycle from 49 and 51 to 48 and 52% (101 to 170 MHz)
Changed the half period jitter from 100 and 100 ps to 75 and 75 ps in the AC
Electrical Specifications table
*B
130114
10/28/03
RGL
Corrected QFN pinouts in the block diagram and in the Pin Description table
*C
210076
See ECN
RGL
Changed the Operating Frequency from 250 MHz to 230 MHz
*D
259010
See ECN
RGL
Changed Half Period Jitter and propagation delay
*E
308437
See ECN
RGL
Added Lead-free devices except the 40 QFN industrial
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