Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

CY7B994V-2AI Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7B994V-2AI
Description  High-speed Multi-phase PLL Clock Buffer
Download  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B994V-2AI Datasheet(HTML) 6 Page - Cypress Semiconductor

Back Button CY7B994V-2AI Datasheet HTML 2Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 3Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 4Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 5Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 6Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 7Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 8Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 9Page - Cypress Semiconductor CY7B994V-2AI Datasheet HTML 10Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 15 page
background image
RoboClock
CY7B993V
CY7B994V
Document #: 38-07127 Rev. *F
Page 6 of 15
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high-impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank will be enabled. When the DIS[1:4]/FBDIS is HIGH, the
outputs for that bank will be disabled to a high-impedance
(HI-Z) or HOLD-OFF state depending on the OUTPUT_MODE
input. Table 5 defines the disabled output functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input (DIS[1:4]/FBDIS) is HIGH. When disabled to the
HOLD-OFF state, non-inverting outputs are driven to a logic
LOW state on its falling edge. Inverting outputs are driven to a
logic HIGH state on its rising edge. This ensures the output
clocks are stopped without glitch. When a bank of outputs is
disabled to HI-Z state, the respective bank of outputs will go
HI-Z immediately.
Note:
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[4]
FBInput
REFInput
–8tU
–7tU
–6tU
–4tU
–3tU
–2tU
–1tU
0t U
+1t U
+2t U
+3t U
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
3F[1:0]
4F[1:0]
(N/A)
LL
LM
LH
ML
MH
MM
HM
HH
(N/A)
(N/A)
(N/A)
1F[1:0]
2F[1:0]
+4tU
+6t U
+7t U
+8t U
HM
HH
HL
(N/A)
(N/A)
Table 5. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
DIS[1:4]/FBDIS
Output Mode
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST


Similar Part No. - CY7B994V-2AI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7B994V-2AI CYPRESS-CY7B994V-2AI Datasheet
292Kb / 14P
   High-Speed Multi-Phase PLL Clock Buffer
More results

Similar Description - CY7B994V-2AI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7B9945V CYPRESS-CY7B9945V Datasheet
110Kb / 10P
   High-speed Multi-phase PLL Clock Buffer
CY7B994V CYPRESS-CY7B994V Datasheet
292Kb / 14P
   High-Speed Multi-Phase PLL Clock Buffer
CY7B993V CYPRESS-CY7B993V_11 Datasheet
586Kb / 18P
   High Speed Multi Phase PLL Clock Buffer
CY7B9945V CYPRESS-CY7B9945V_07 Datasheet
261Kb / 11P
   High Speed Multi-phase PLL Clock Buffer
CY7B9945V CYPRESS-CY7B9945V_11 Datasheet
430Kb / 15P
   High Speed Multi-phase PLL Clock Buffer
CY7B9930V CYPRESS-CY7B9930V Datasheet
158Kb / 9P
   High-Speed Multi-Frequency PLL Clock Buffer
CY7B9973V CYPRESS-CY7B9973V Datasheet
167Kb / 8P
   High-Speed Multi-Output PLL Clock Buffer
CY7B995 CYPRESS-CY7B995_07 Datasheet
383Kb / 13P
   2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950 CYPRESS-CY7B9950_07 Datasheet
331Kb / 12P
   2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950 CYPRESS-CY7B9950_06 Datasheet
296Kb / 10P
   2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com