RoboClock®, CY7B995
Document #: 38-07337 Rev. *D
Page 3 of 13
Table 1. Pin Definitions - 44 Pin TQFP Package
Device Configuration
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback input
divider is controlled by the 3-level DS[0:1] pins as indicated in
Table 3 on page 4, and the reference input divider is controlled
by the 3-level PD#/DIV pin as indicated in Table 2.
Table 2. Reference Divider Settings
Pin
Name
IO[1]
Type
Description
39
REF
I
LVTTL/LVCMOS
Reference Clock Input.
17
FB
I
LVTTL
Feedback Input.
37
TEST
I
3-Level
When MID or HIGH, disables PLL[3]. REF goes to all outputs. Set LOW
for normal operation.
2
sOE#
I, PD LVTTL
Synchronous Output Enable. When HIGH, it stops clock outputs
(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0, and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW
for normal operation.
4
PE/HD
I, PU 3-Level
Selects Positive or Negative Edge Control, and High or Low output
Drive Strength. When LOW/HIGH, the outputs are synchronized with the
negative/positive edge of the reference clock respectively. When at MID
level, the output drive strength is increased and the outputs synchronize
with the positive edge of the reference clock. See Table 10 on page 5.
34, 33, 36, 35,
43, 42, 1, 44
nF[1:0]
I
3-Level
Selects Frequency and Phase of the Outputs. See Table 4, Table 5,
Table 6, Table 8, and Table 9 on page 4.
41
FS
I
3-Level
Selects VCO Operating Frequency Range. See Table 7 on page 4.
26,27,20,21,
13,14,7,8
nQ[1:0]
O
LVTTL
Four banks of two outputs. See Table 6 on page 4 for frequency
settings.
32, 31
DS[1:0]
I
3-Level
Selects Feedback Divider. See Table 3 on page 4.
3
PD#/DIV
I, PU 3-Level
Power down and Reference Divider Control. When LOW, shuts off
entire chip. When at MID level, enables the reference divider. See Table 2
for settings.
30
LOCK
O
LVTTL
PLL Lock Indication Signal. HIGH indicates lock, LOW indicates the
PLL is not locked, and outputs may not be synchronized to the input.
5,6
VDDQ4
[2]
PWR Power
Power supply for Bank 4 Output Buffers. See Table 11 on page 5 for
supply level constraints.
15,16
VDDQ3
[2]
PWR Power
Power supply for Bank 3 Output Buffers. See Table 11 on page 5 for
supply level constraints.
19,28,29
VDDQ1
[2]
PWR Power
Power supply for Bank 1 and Bank 2 Output Buffers. See Table 11 on
page 5 for supply level constraints.
18,40
VDD
[2]
PWR Power
Power supply for the Internal Circuitry. See Table 11 on page 5 for
supply level constraints.
9-12, 22-25, 38 VSS
PWR Power
Ground
PD#/DIV
R–Reference Divider
H1
M2
L[4]
N/A
Notes
1. PD indicates an internal pull down and ‘PU’ indicates an internal pull up.
2. A bypass capacitor (0.1
μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic is cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. When PD#/DIV = LOW, the device enters power down mode.
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