High-speed Multi-phase PLL Clock Buffer
RoboClock
CY7B993V
CY7B994V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07127 Rev. *F
Revised August 10, 2005
Features
• 500-ps max. Total Timing Budget™ (TTB™) window
• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)
input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 18 LVTTL outputs driving 50
Ω terminated lines
• 16 outputs at 200 MHz: Commercial temperature
• 6 outputs at 200 MHz: Industrial temperature
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable
reference inputs
• Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns
• Multiply/divide ratios of 1–6, 8, 10, 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Fully integrated phase-locked loop (PLL) with lock
indicator
• <50-ps typical cycle-to-cycle jitter
• Single 3.3V ± 10% supply
• 100-pin TQFP package
• 100-lead BGA package
Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the
system integrator with functions necessary to optimize the
timing of high-performance computer and communication
systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated trans-
mission lines with impedances as low as 50
Ω while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in five banks. Banks 1 to 4 of four outputs allow
a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625–1300-ps increments up to 10.4 ns.
One of the output banks also includes an independent clock
invert function. The feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12 and limited
phase adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change-over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
FS
OUTPUT_MODE
FBF0
FBDS0
FBDS1
FBDIS
4F0
4F1
4DS0
4DS1
DIS4
3F0
3F1
3DS0
3DS1
DIS3
2F0
2F1
2DS0
2DS1
DIS2
1F0
1F1
1DS0
1DS1
DIS1
QFA0
QFA1
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
LOCK
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
3
INV3
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Phase
Freq.
Detector
Filter
VCO
Control Logic
Divide and Phase
Generator
Feedback Bank
Bank 4
Bank 3
Bank 2
Bank 1
Functional
Block Diagram
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