CY7B923
CY7B933
Document #: 38-02017 Rev. *E
Page 11 of 33
BIST Mode
BIST mode functions as follows:
1. Set BISTEN LOW to begin test pattern generation. Trans-
mitter begins sending bit rate ...1010...
2. Set either ENA or ENN LOW to begin pattern sequence
generation (use of the Enable pin not being used for normal
FIFO or system interface can minimize logic delays
between the controller and transmitter).
3. Allow the Transmitter to run through several BIST loops or
until the Receiver test is complete. RP will pulse LOW once
per BIST loop, and can be used by an external counter to
monitor the number of test pattern loops.
4. When testing is completed, set BISTEN HIGH and ENA and
ENN HIGH and resume normal function.
Note: It may be advisable to send violation characters to test
the RVS output in the Receiver. This can be done by explicitly
sending a violation with the SVS input, or allowing the trans-
mitter BIST loop to run while the Receiver runs in normal
mode. The BIST loop includes deliberate violation symbols
and will adequately test the RVS function.
Figure 6. BIST Illustration
FOTO
MODE
CKW
RP
SC/D
D0–7
SVS
ENA
ENN
BISTEN
REFCLK
MODE
RF
CKR
SC/D
Q0–7
RVS
RDY
BISTEN
OUTA
OUTB
OUTC
DON'T CARE
SO
INA
INB
A/B
CY7B923
CY7B933
8
8
BIST
Tx
START
Tx
STOP
ERROR
TEST
START
TEST
END
Rx
BEGIN
LOOP
BIST
LOOP
TEST
LOW
DON'T CARE
LOW
WITHIN SPEC.
DON'T CARE
LOW
DON'T CARE
WITHIN SPEC.
DON'T CARE
DON'T CARE
HIGH
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