CY7C008V/009V
CY7C018V/019V
Document #: 38-06044 Rev. *C
Page 6 of 18
Switching Characteristics Over the Operating Range[10]
Parameter
Description
CY7C008V/009V
CY7C018V/019V
Unit
-15
-20
-25
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
15
20
25
ns
tAA
Address to Data Valid
15
20
25
ns
tOHA
Output Hold From Address Change
3
3
3
ns
tACE[11]
CE LOW to Data Valid
15
20
25
ns
tDOE
OE LOW to Data Valid
10
12
13
ns
tLZOE[12, 13, 14] OE LOW to Low Z
3
3
3
ns
tHZOE[12, 13, 14] OE HIGH to High Z
10
12
15
ns
tLZCE[12, 13, 14] CE LOW to Low Z
3
3
3
ns
tHZCE[12, 13, 14] CE HIGH to High Z
10
12
15
ns
tPU[14]
CE LOW to Power-Up
0
0
0
ns
tPD[14]
CE HIGH to Power-Down
15
20
25
ns
tABE[11]
Byte Enable Access Time
15
20
25
ns
WRITE CYCLE
tWC
Write Cycle Time
15
20
25
ns
tSCE[11]
CE LOW to Write End
12
16
20
ns
tAW
Address Valid to Write End
12
16
20
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA[11]
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
12
17
22
ns
tSD
Data Set-Up to Write End
10
12
15
ns
tHD
Data Hold From Write End
0
0
0
ns
tHZWE[13, 14]
R/W LOW to High Z
10
12
15
ns
tLZWE[13, 14]
R/W HIGH to Low Z
3
3
3
ns
tWDD[15]
Write Pulse to Data Delay
30
40
50
ns
tDDD[15]
Write Data Valid to Read Data Valid
25
30
35
ns
BUSY TIMING[16]
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
BUSY LOW from CE LOW
152020
ns
tBHC
BUSY HIGH from CE HIGH
15
16
17
ns
tPS
Port Set-Up for Priority
5
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
000
ns
Notes:
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
11. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
13. Test conditions used are Load 2.
14. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Read Timing with Busy waveform.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. Test conditions used are Load 1.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
