DS1284/DS1286

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OPERATION—READ REGISTERS

The DS1284/DS1286 execute a read cycle whenever

WE (write enable) is inactive (high) and CE (chip

enable) and

OE (output enable) are active (low). The unique address specified by the six address inputs

(A0–A5) defines which of the 64 registers is to be accessed. Valid data is available to the eight data

OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be

measured from the latter occurring signal (

for

OE rather than address access.

OPERATION—WRITE REGISTERS

The DS1284/DS1286 are in the write mode whenever the

WE and CE signals are in the active-low state

after the address inputs are stable. The latter occurring falling edge of

CE or WE determines the start of

the write cycle. The write cycle is terminated by the earlier rising edge of

CE or WE. All address inputs

must be kept valid throughout the write cycle.

WE must return to the high state for a minimum recovery

signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output

bus has been enabled (

DATA RETENTION

protects itself, and all inputs to the registers become “don’t care.” Both

INTA and INTB (INTB) are

open-drain outputs. The two interrupts and the internal clock continue to run regardless of the level of

circuit turns on the lithium energy source to maintain the clock and timer data functionality. Also ensure

that during this time (battery-backup mode), the voltage present at

INTA and INTB (INTB) never

exceeds the battery voltage. If the active-high mode is selected for

INTB (INTB), this pin only goes high

WATCHDOG TIMEKEEPER REGISTERS

The watchdog timekeeper has 64 8-bits-wide registers that contain all the timekeeping, alarm, watchdog,

control, and data information. The clock, calendar, alarm, and watchdog registers are memory locations

that contain external (user-accessible) and internal copies of the data. The external copies are independent

of internal functions, except that they are updated periodically by the simultaneous transfer of the

incremented internal copy (see Figure 1). The command register bits are affected by both internal and

external functions. This register is discussed later. The 50 bytes of RAM registers can only be accessed

from the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day and date

information (see Figure 2). Time-of-day information is stored in binary-coded decimal (BCD). Registers

3, 5, and 7 contain the time-of-day alarm information. Time-of-day alarm information is stored in BCD.

Register B is the command register and information in this register is binary. Registers C and D are the

watchdog alarm registers and information stored in these two registers is in BCD. Registers E to 3F are

user bytes and can be used to contain data at the user’s discretion.