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CY7C138
CY7C139
Document #: 38-06037 Rev. *B
Page 7 of 16
Read Timing with Port-to-Port Delay (M/S = L)[20, 21]
Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[22, 23, 24]
Notes:
20. BUSY = HIGH for the writing port.
21. CEL = CER = LOW.
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
pulse can be as short as the specified tPWE.
24. R/W must be HIGH during all address transitions.
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESS R
t
PWE
VALID
t
SD
t
HD
ADDRESS L
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE
t
LZOE
SEM OR CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
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