RoboClock
CY7B993V
CY7B994V
Document #: 38-07127 Rev. *F
Page 7 of 15
INV3 Pin Function
Bank3 has signal invert capability. The four outputs of Bank3
will act as two pairs of complementary outputs when the INV3
pin is driven LOW. In complementary output mode, 3QA0 and
3QB0 are non-inverting; 3QA1and 3QB1 are inverting outputs.
All four outputs will be inverted when the INV3 pin is driven
HIGH. When the INV3 pin is left in MID, the outputs will not
invert. Inversion of the outputs are independent of the skew
and divide functions. Therefore, clock outputs of Bank3 can be
inverted, divided, and skewed at the same time.
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH,
a “Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time out period is based upon a divided down reference
clock.
This assumes that there is activity on the selected REF input.
If there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal
PLL.
Factory Test Mode Description
The device will enter factory test mode when the
OUTPUT_MODE is driven to MID. In factory test mode, the
device will operate with its internal PLL disconnected; input
level supplied to the reference input will be used in place of the
PLL output. In TEST mode the selected FB input(s) must be
tied LOW. All functions of the device are still operational in
factory test mode except the internal PLL and output bank
disables. The OUTPUT_MODE input is designed to be a static
input. Dynamically toggling this input from LOW to HIGH may
temporarily cause the device to go into factory test mode
(when passing through the MID state).
Factory Test Reset
When in factory test mode (OUTPUT_MODE = MID), the
device can be reset to a deterministic state by driving the DIS4
input HIGH. When the DIS4 input is driven HIGH in factory test
mode, all clock outputs will go to HI-Z; after the selected
reference clock pin has five positive transitions, all the internal
finite state machines (FSM) will be set to a deterministic state.
The deterministic state of the state machines will depend on
the configurations of the divide selects, skew selects, and
frequency select input. All clock outputs will stay in
high-impedance mode and all FSMs will stay in the determin-
istic state until DIS4 is deasserted. When DIS4 is deasserted
(with OUTPUT_MODE still at MID), the device will re-enter
factory test mode.
Safe Operating Zone
Figure 2 illustrates the operating condition at which the device
does not exceed its allowable maximum junction temperature
of 150°C. Figure 2 shows the maximum number of outputs that
can operate at 185 MHz (with 25-pF load and no air flow) or
200 MHz (with 10-pF load and no air flow) at various ambient
temperatures. At the limit line, all other outputs are configured
to divide-by-two (i.e., operating at 92.5 MHz) or lower
frequencies. The device will operate below maximum
allowable junction temperature of 150°C when its configu-
ration (with the specified constraints) falls within the shaded
region (safe operating zone). Figure 2 shows that at 85°C, the
maximum number of outputs that can operate at 200 MHz is
6; and at 70°C, the maximum number of outputs that can
operate at 185 MHz is 16 (with 25-pF load and 0-m/s air flow).
Typical Safe Operating Zone
(25-pF Load, 0-m/s air flow )
50
55
60
65
70
75
80
85
90
95
100
2468
10
12
14
16
18
Number of Outputs at 185 MHz
Safe Operating Zone
Figure 2. Typical Safe Operating Zone
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