CY7C138
CY7C139
Document #: 38-06037 Rev. *B
Page 5 of 16
Switching Characteristics Over the Operating Range[9]
Parameter
Description
7C138-15
7C139-15
7C138-25
7C139-25
7C138-35
7C139-35
7C138-55
7C139-55
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
15
25
35
55
ns
tAA
Address to Data Valid
15
25
35
55
ns
tOHA
Output Hold From Address Change
3
3
3
3
ns
tACE
CE LOW to Data Valid
15
25
35
55
ns
tDOE
OE LOW to Data Valid
10
15
20
25
ns
tLZOE[10,11,12] OE Low to Low Z
3
3
3
3
ns
tHZOE[10,11,12] OE HIGH to High Z
10
15
20
25
ns
tLZCE[10,11,12] CE LOW to Low Z
3
3
3
3
ns
tHZCE[10,11,12] CE HIGH to High Z
10
15
20
25
ns
tPU[12]
CE LOW to Power-Up
0
0
0
0
ns
tPD[12]
CE HIGH to Power-Down
15
25
35
55
ns
WRITE CYCLE
tWC
Write Cycle Time
15
25
35
55
ns
tSCE
CE LOW to Write End
12
20
30
40
ns
tAW
Address Set-Up to Write End
12
20
30
40
ns
tHA
Address Hold From Write End
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
30
ns
tSD
Data Set-Up to Write End
10
15
15
20
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[11,12]
R/W LOW to High Z
10
15
20
25
ns
tLZWE[11,12]
R/W HIGH to Low Z
3
3
3
3
ns
tWDD[13]
Write Pulse to Data Delay
30
50
60
70
ns
tDDD[13]
Write Data Valid to Read Data Valid
25
30
35
40
ns
BUSY TIMING[14]
tBLA
BUSY LOW from Address Match
15
20
20
45
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
40
ns
tBLC
BUSY LOW from CE LOW
15
20
20
40
ns
tBHC
BUSY HIGH from CE HIGH
15
20
20
35
ns
tPS
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/W LOW after BUSY LOW
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
40
ns
tBDD[15]
BUSY HIGH to Data Valid
Note 15
Note 15
Note 15
Note 15
ns
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
