CY7C188
Document #: 38-05053 Rev. *A
Page 3 of 7
AC Test Loads and Waveforms[4, 5]
3.0V
5V
OUTPUT
R1 481
Ω
R2
255
Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
5V
OUTPUT
R1 481
Ω
R2
255
Ω
5pF
INCLUDING
JIGAND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THÉVENIN EQUIVALENT
ALLINPUTPULSES
C188–3
C188–4
167
Ω
Switching Characteristics Over the Operating Range[2, 4]
–15
–20
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
20
ns
tAA
Address to Data Valid
15
20
ns
tOHA
Data Hold from Address Change
3
3
ns
tACE
CE1 LOW or CE2 HIGH to Data Valid
15
20
ns
tDOE
OE LOW to Data Valid
7
9
ns
tLZOE
OE LOW to Low Z[6]
0
0
ns
tHZOE
OE HIGH to High Z[5,6]
7
9
ns
tLZCE
CE1 LOW or CE2 HIGH to Low Z
[6]
3
3
ns
tHZCE
CE1 HIGH or CE2 LOW to High Z
[5, 6]
7
9
ns
tPU
CE1 LOW or CE2 HIGH to Power-Up
0
0
ns
tPD
CE1 HIGH or CE2 LOW to Power-Down
15
20
ns
WRITE CYCLE[7, 8]
tWC
Write Cycle Time
15
20
ns
tSCE
CE1 LOW or CE2 HIGH to Write End
10
15
ns
tAW
Address Set-Up to Write End
10
15
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
10
15
ns
tSD
Data Set-Up to Write End
8
10
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High Z[5]
0
7
0
7
ns
tLZWE
WE HIGH to Low Z[5, 6]
3
3
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE1, LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write and any
signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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