RoboClock
CY7B993V
CY7B994V
Document #: 38-07127 Rev. *F
Page 6 of 15
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high-impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank will be enabled. When the DIS[1:4]/FBDIS is HIGH, the
outputs for that bank will be disabled to a high-impedance
(HI-Z) or HOLD-OFF state depending on the OUTPUT_MODE
input. Table 5 defines the disabled output functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input (DIS[1:4]/FBDIS) is HIGH. When disabled to the
HOLD-OFF state, non-inverting outputs are driven to a logic
LOW state on its falling edge. Inverting outputs are driven to a
logic HIGH state on its rising edge. This ensures the output
clocks are stopped without glitch. When a bank of outputs is
disabled to HI-Z state, the respective bank of outputs will go
HI-Z immediately.
Note:
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[4]
FBInput
REFInput
–8tU
–7tU
–6tU
–4tU
–3tU
–2tU
–1tU
0t U
+1t U
+2t U
+3t U
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
3F[1:0]
4F[1:0]
(N/A)
LL
LM
LH
ML
MH
MM
HM
HH
(N/A)
(N/A)
(N/A)
1F[1:0]
2F[1:0]
+4tU
+6t U
+7t U
+8t U
HM
HH
HL
(N/A)
(N/A)
Table 5. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
DIS[1:4]/FBDIS
Output Mode
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST