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CY7C132/CY7C136
CY7C142/CY7C146
Document #: 38-06031 Rev. *C
Page 7 of 18
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[19, 20]
Read Cycle No. 2 (Either Port-CE/OE)[19, 21]
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
21. Address valid prior to or coincident with CE transition LOW.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSYL
DOUTL
tPS
tBLA
tRC
tPWE
VALID
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