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CY7C144
CY7C145
Document #: 38-06034 Rev. *C
Page 8 of 20
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[15, 16]
Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18]
Read Timing with Port-to-Port Delay (M/S=L)[19, 20]
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
DATA OUT
SEM or CE
OE
tLZCE
tPU
ICC
ISB
tPD
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATAINR
DATAOUTL
tWC
ADDRESSR
t
PWE
VALID
t
SD
t
HD
ADDRESSL
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