CY7C1011CV33
Document Number: 38-05232 Rev. *F
Page 6 of 14
Switching Characteristics
Over the Operating Range [4]
Parameter
Description
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle
tpower
[5]
VCC(Typical) to the First Access
1
1
1
μs
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low Z[6]
000
ns
tHZOE
OE HIGH to High Z[6, 7]
567
ns
tLZCE
CE LOW to Low Z[6]
333
ns
tHZCE
CE HIGH to High Z[6, 7]
567
ns
tPU
CE LOW to Power Up
0
0
0
ns
tPD
CE HIGH to Power Down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low Z
0
0
0
ns
tHZBE
Byte Disable to High Z
5
6
7
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
7
8
10
ns
tAW
Address Setup to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Setup to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Setup to Write End
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[6]
333
ns
tHZWE
WE LOW to High Z[6, 7]
567
ns
tBW
Byte Enable to End of Write
7
8
10
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 5. Transition is measured ±500
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
