CY7C1012DV33
Document Number: 38-05610 Rev. *C
Page 5 of 10
AC Switching Characteristics
Over the Operating Range [5]
Parameter
Description
–8
Unit
Min
Max
Read Cycle
tpower [6]
VCC(Typical) to the First Access
100
µs
tRC
Read Cycle Time
8
ns
tAA
Address to Data Valid
8
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE Active LOW to Data Valid [3]
8ns
tDOE
OE LOW to Data Valid
5
ns
tLZOE
OE LOW to Low Z [7]
1ns
tHZOE
OE HIGH to High Z [7]
5ns
tLZCE
CE Active LOW to Low Z [3, 7]
3ns
tHZCE
CE Deselect HIGH to High Z [3, 7]
5ns
tPU
CE Active LOW to Power Up [3, 8]
0ns
tPD
CE Deselect HIGH to Power Down [3, 8]
8ns
Write Cycle [9, 10]
tWC
Write Cycle Time
8
ns
tSCE
CE Active LOW to Write End [3]
6ns
tAW
Address Setup to Write End
6
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
6
ns
tSD
Data Setup to Write End
5
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z [7]
3ns
tHZWE
WE LOW to High Z [7]
5ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of AC Test Loads and Waveforms, unless specified otherwise.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±200
mV from steady state voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate
a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
