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CY7C130/CY7C131
CY7C140/CY7C141
Document #: 38-06002 Rev. *D
Page 8 of 19
Switching Waveforms
Read Cycle No. 1[19, 20]
Read Cycle No. 2[19, 21]
Read Cycle No. 3[20]
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
21. Address valid prior to or coincident with CE transition LOW.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATAVALID
DATA OUT
ADDRESS
Either Port Address Access
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
Either Port CE/OE Access
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSYL
DOUTL
tPS
tBLA
Read with BUSY, Master: CY7C130 and CY7C131
tRC
tPWE
VALID
tHD
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