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CY7C130/CY7C131
CY7C140/CY7C141
Document #: 38-06002 Rev. *D
Page 9 of 19
Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[15, 22]
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23]
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
CE
R/W
ADDRESS
tHZOE
OE
DOUT
DATAIN
Either Port
tAW
tWC
tSCE
tSA
tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
DATA VALID
tLZWE
ADDRESS
CE
R/W
DATAOUT
DATAIN