DS1558

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Figure 4. BACKUP MODE ALARM WAVEFORMS

USING THE WATCHDOG TIMER

The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog

timer by setting the desired amount of timeout into the 8-bit watchdog register (address 7FFF7h). The

five watchdog register bits BMB4–BMB0 store a binary multiplier and the two lower-order bits

RB1–RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and

11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit

multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the watchdog register

= 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the

watchdog flag (WF) is set and a processor interrupt is generated and stays active until either WF is read

or the watchdog register (7FFF7h) is read or written.

The MSB of the watchdog register is the watchdog steering bit (WDS). When set to a 0, the watchdog

be initialized to a 0 if the watchdog function is enabled.

The watchdog timer resets when the processor performs a read or write of the watchdog register. The

timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to the watchdog

register. The watchdog function is automatically disabled upon power-up and the watchdog register is

cleared.

POWER-ON DEFAULT STATES

Upon application of power to the device, the following register bits are set to a 0:

WDS = 0, BMB0–BMB4 = 0, RB0–RB1 = 0, AE = 0, and ABE = 0

All other bits are undefined.