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DS1558Y+TRL Datasheet(PDF) 6 Page - Maxim Integrated Products |
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DS1558Y+TRL Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 18 page  DS1558 6 of 18 DATA WRITE MODE The DS1558 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE then disables the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC is below the power-fail point VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGIVITY The battery lifetime is dependent on the RAM battery standby current and the DS1558 internal clock oscillator current. The total battery current is IOSC + ICCO. When VCC is above VPF, IBAT current is less than 50nA. The DS1558 has an internal circuit to prevent battery charging. No external protection components are required, and none should be used. The DS1558 has two battery pins that operate independently; the DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to VBAT1, and VBAT2 should be grounded. INTERNAL BATTERY MONITOR The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF) bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the power- fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled. |
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