CY7C1041CV33
Document Number: 38-05134 Rev. *I
Page 6 of 14
Switching Characteristics
Over the Operating Range [4]
Parameter
Description
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle
tpower
[5]
VCC(Typical) to the First Access
100
100
100
100
μs
tRC
Read Cycle Time
10
12
15
20
ns
tAA
Address to Data Valid
10
12
15
20
ns
tOHA
Data Hold from Address Change
3333
ns
tACE
CE LOW to Data Valid
10121520
ns
tDOE
OE LOW to Data Valid
Comm’l/Ind’l/Auto-A
5678
ns
Auto-E
7
8
tLZOE
OE LOW to Low Z[6]
0000
ns
tHZOE
OE HIGH to High Z[6, 7]
5678
ns
tLZCE
CE LOW to Low Z[6]
3333
ns
tHZCE
CE HIGH to High Z[6, 7]
5678
ns
tPU
CE LOW to Power Up
0000
ns
tPD
CE HIGH to Power Down
10
12
15
20
ns
tDBE
Byte Enable to Data Valid
Comm’l/Ind’l/Auto-A
5678
ns
Auto-E
7
8
tLZBE
Byte Enable to Low Z
0000
ns
tHZBE
Byte Disable to High Z
6678
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
7
8
10
10
ns
tAW
Address Setup to Write End
7
8
10
10
ns
tHA
Address Hold from Write End
0000
ns
tSA
Address Setup to Write Start
0000
ns
tPWE
WE Pulse Width
7
8
10
10
ns
tSD
Data Setup to Write End
5678
ns
tHD
Data Hold from Write End
0000
ns
tLZWE
WE HIGH to Low Z[6]
3333
ns
tHZWE
WE LOW to High Z[6, 7]
5678
ns
tBW
Byte Enable to End of Write
7
8
10
10
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms on page 5. Transition is measured ±500
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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