16-Mbit (2M x 8) Static RAM
CY7C1069BV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05694 Rev. *B
Revised August 3, 2006
Features
•High speed
—tAA = 10 ns
• Low active power
— 990 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Available in Pb-free and non Pb-free 54-pin TSOP II
package
Functional Description
The CY7C1069BV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
LOW) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE LOW) as well as forcing the Output Enable (OE) LOW
while forcing the Write Enable (WE) HIGH. See the truth table
at the back of this data sheet for a complete description of
Read and Write modes.
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW and WE LOW).
The CY7C1069BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
2M x 8
ARRAY
A0
I/O0–I/O7
OE
WE
CE
A9
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
43
42
16
15
29
30
A5
A6
A7
A8
A0
A1
OE
VSS
A17
I/O7
A2
I/O0
I/O1
A3
A4
18
17
20
19
27
28
25
26
22
21
23
24
I/O2
I/O3
A16
A15
VCC
I/O6
NC
I/O5
I/O4
A14
A13
A12
A11
A9
A10
44
46
45
47
50
49
48
51
53
52
54
VSS
VCC
A19
A18
VCC
VCC
VSS
VSS
NC
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
A20
CE
DNU/VCC
DNU/VSS
54-pin TSOP II (Top View)
Pin Configurations[1, 2]
Notes:
1. DNU/VCC Pin (#16) has to be left floating or connected to VCC and DNU/VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application.
2. NC - No Connect Pins are not connected to the die.
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