Real-Time Clock

10

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Pin Description (continued)

PIN

SO,

PDIP

EDIP

PLCC

TQFP

NAME

FUNCTION

19

19

23

21

IRQ

Active-Low Interrupt Request Output. The IRQ pin is an active-low output of the

device that can be used as an interrupt input to a processor. The IRQ output

remains low as long as the status bit causing the interrupt is present and the

corresponding interrupt-enable bit is set. The processor program normally

reads the C register to clear the IRQ pin. The RESET pin also clears pending

interrupts. When no interrupt conditions are present, the IRQ level is in the high-

impedance state. Multiple interrupting devices can be connected to an IRQ

bus, provided that they are all open drain. The IRQ pin is an open-drain output

20

—

24

22

Connection for a Primary Battery. (DS12885 Only.) Battery voltage must be held

between the minimum and maximum limits for proper operation. If a backup

prevent proper operation. UL recognized to ensure against reverse charging

when used with a lithium battery.

21

21

(DS12887A/

DS12C887A)

25

24

RCLR

Active-Low RAM Clear. The RCLR pin is used to clear (set to logic 1) all the

general-purpose RAM, but does not affect the RAM associated with the RTC. To

clear the RAM, RCLR must be forced to an input logic 0 during battery-backup

through a human interface (shorting to ground manually or by a switch) and not

to be driven with external buffers. This pin is internally pulled up. Do not use an

external pullup resistor on this pin.

23

23

27

26

SQW

Square-Wave Output. The SQW pin can output a signal from one of 13 taps

provided by the 15 internal divider stages of the RTC. The frequency of the

SQW pin can be changed by programming Register A, as shown in Table 1.

The SQW signal can be turned on and off using the SQWE bit in Register B. The

24

24

28

28

limits, the device is fully accessible and data can be written and read. When