RTC with Constant-Voltage Trickle Charger

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9

POWER

CONTROL

AND

TRICKLE

CHARGER

OSC

BUS

INTERFACE

X1

X2

DS12R887/

DS12CR887

ONLY

DS12R887/

DS12CR887

ONLY

RESET

CS

DS

AS

R/W

MOT

AD0–AD7

DIVIDE

BY 8

DIVIDE

BY 64

DIVIDE

BY 64

16:1 MUX

SQUARE-

WAVE

GENERATOR

REGISTERS A, B, C, D

CLOCK/CALENDAR AND

ALARM REGISTERS

USER RAM

114 BYTES

CLOCK/CALENDAR

UPDATE LOGIC

IRQ

SQW

IRQ

GENERATOR

BUFFERED CLOCK/

CALENDAR AND ALARM

REGISTERS

GND

RLCR

DS12R885

Functional Diagram

Pin Description

PIN

SO

EDIP

BGA

NAME

FUNCTION

1

1

C5

MOT

Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When

disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor.

2—

—

X1

3—

—

X2

Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is

X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz

oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is

connected to pin X1.

4–11

4–11

F4, D4,

F3, D3,

F2, D2,

F1, D1

AD0–

AD7

Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first

portion of the bus cycle and latched into the DS12R885 by the falling edge of AS. Write

data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel

timing). In a read cycle, the DS12R885 outputs data during the latter portion of DS (DS and

R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is

terminated and the bus returns to a high-impedance state as DS transitions low in the case

of Motorola timing or as DS transitions high in the case of Intel timing.