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CY7C1302DV25 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1302DV25
Description  9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1302DV25 Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY7C1302DV25
Document #: 38-05625 Rev. *A
Page 9 of 18
TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range [10, 13, 15]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.7
V
VOH2
Output HIGH Voltage
IOH = −100 µA2.1
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.7
V
VOL2
Output LOW Voltage
IOL = 100 µA0.2
V
VIH
Input HIGH Voltage
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.7
V
IX
Input and Output Load Current
GND
≤ V
I ≤ VDDQ
–5
5
µA
TAP AC Switching Characteristics Over the Operating Range [11, 12]
Parameter
Description
Min.
Max.
Unit
tTCYC
TCK Clock Cycle Time
50
ns
tTF
TCK Clock Frequency
20
MHz
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Notes:
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. TCS and TCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
106
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS


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