CY7C1298A/
GVT7164C18
Document #: 38-05194 Rev. *A
Page 7 of 12
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Unit
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
4-layer PCB
Θ
JA
20
°C/W
Thermal Resistance (Junction to Case)
Θ
JC
1
°C/W
AC Test Loads and Waveforms[23]
3.0V
0V
90%
10%
90%
10%
≤ 1.5 ns
≤ 1.5 ns
(a)
(b)
ALL INPUT PULSES
DQ
+3.3v
317
Ω
351
Ω
5 pF
Vt = 1.5V
30 pF
DQ
Z
0 = 50Ω
50
Ω
V ccm in
Vc c ty p
t PU = 200us
F or prope r R E S E T
bring V c c dow n t o 0V
(c)
(d)
Capacitance Derating[23]
Description
Symbol
Typ.
Max.
Unit
Clock to output valid
∆ tKQ
0.016
ns / pF
Switching Characteristics Over the Operating Range[25]
Parameter
Description
100 MHz
-5
83 MHz
-6
66 MHz
-7
50 MHz
-8
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock
tKC
Clock Cycle Time
10
12
15
20
ns
tKH
Clock HIGH Time
4
4
5
6
ns
tKL
Clock LOW Time
44
56
ns
Output Times
tKQ
Clock to Output Valid
5
6
7
8
ns
tKQX
Clock to Output Invalid
2
2
2
2
ns
tKQLZ
Clock to Output in Low-Z[26, 27]
33
33
ns
tKQHZ
Clock to Output in High-Z[26, 27]
55
66
ns
tOEQ
OE to Output Valid[28]
55
56
ns
tOELZ
OE to Output in Low-Z[26, 27]
00
00
ns
tOEHZ
OE to Output in High-Z[26, 27]
45
66
ns
Set-up Times
tS
Address, Controls, and Data In[29]
2.5
2.5
2.5
3
ns
Hold Times
tH
Address, Controls, and Data In[29]
0.5
0.5
0.5
0.5
ns
Notes:
23. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for
t<200 ms.
24. Capacitance derating applies to capacitance different from the load capacitance shown in part (a) of AC Test Loads.
25. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
26. Output loading is specified with CL = 5 pF as in AC Test Loads.
27. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
28. OE is a “don’t care” when a byte write enable is sampled LOW.
29. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table.
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