CY7C1305AV18 datasheet(2/20 Pages) CYPRESS

Part #	CY7C1305AV18

Description	18-Mb Burst of 4 Pipelined SRAM with QDR??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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PRELIMINARY

CY7C1305AV18

CY7C1307AV18

Document #: 38-05495 Rev. *A

Page 2 of 20

Selection Guide

CY7C1305AV18-167

CY7C1307AV18-167

CY7C1305AV18-133

CY7C1307AV18-133

CY7C1305AV18-100

CY7C1307AV18-100

Unit

Maximum Operating Frequency

167

133

100

MHz

Maximum Operating Current

650

620

590

mA

Pin Configuration–CY7C1305AV18 (Top View)

1

2

3

4

56789

10

11

A

NC

Gnd/144M NC/36M

WPS

BWS1

K

NC

RPS

A

Gnd/72M

NC

B

NC

Q9

D9

A

NC

K

BWS0

ANC

NC

Q8

C

NC

D10

VSS

A

NC

A

VSS

NC

Q7

D8

D

NC

D11

Q10

VSS

NC

D7

E

NC

Q11

VDDQ

VSS

VDDQ

NC

D6

Q6

F

NC

Q12

D12

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q5

G

NC

D13

Q13

VDDQ

VDD

VSS

VDD

VDDQ

NC

D5

H

NC

VREF

VDDQ

VDD

VSS

VDD

VDDQ

VREF

ZQ

J

NC

D14

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q4

D4

K

NC

Q14

VDDQ

VDD

VSS

VDD

VDDQ

NC

D3

Q3

L

NC

Q15

D15

VDDQ

VSS

VDDQ

NC

Q2

M

NC

D16

VSS

NC

Q1

D2

N

NC

D17

Q16

VSS

A

VSS

NC

D1

P

NC

Q17

A

C

A

NC

D0

Q0

R

TDO

TCK

AAA

C

AA

A

TMS

TDI

Pin Configuration–CY7C1307AV18 (Top View)

1

2

3

456

7

8

9

10

11

A

NC

Gnd/288M NC/ 72M

WPS

BWS2

K

BWS1

RPS

NC/36M Gnd/144M

NC

B

Q27

Q18

D18

A

BWS3

KBWS0

AD17

Q17

Q8

C

D27

Q28

D19

VSS

A

NC

A

VSS

D16

Q7

D8

D

D28

D20

Q19

VSS

Q16

D15

D7

Logic Block Diagram (CY7C1307AV18)

CLK

A(16:0)

Gen.

K

Control

Logic

Address

Register

D[35:0]

Read Data Reg.

RPS

WPS

Q[35:0]

Control

Logic

Address

Register

Reg.

72

17

36

144

36

BWS[0:3]

Vref

Write

Reg

72

A(16:0)

17

C

Write

Reg

Write

Reg

Write

Reg

36

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