2 / 20 page
PRELIMINARY
CY7C1305BV18
CY7C1307BV18
Document #: 38-05629 Rev. **
Page 2 of 20
Logic Block Diagram (CY7C1305BV18)
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS[0:1]
Vref
Write
Reg
36
A(17:0)
18
C
C
Write
Reg
Write
Reg
Write
Reg
18
Logic Block Diagram (CY7C1307BV18)
CLK
A(16:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS[0:3]
Vref
Write
Reg
72
A(16:0)
17
C
C
Write
Reg
Write
Reg
Write
Reg
36