PRELIMINARY
CY7C1317AV18
CY7C1319AV18
CY7C1321AV18
Document #: 38-05500 Rev. *B
Page 4 of 20
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input/Output-
Synchronous
Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When Read access is deselected, Q[x:0] are automatically three-stated.
CY7C1317AV18 - DQ[7:0]
CY7C1319AV18 - DQ[17:0]
CY7C1321AV18 - DQ[35:0]
LD
Input-
Synchronous
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst of 4
data (two clock periods of bus activity).
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
− active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1317AV18
− BWS0 controls D[3:0] and BWS1 controls D[7:4].
CY7C1319AV18
− BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1321AV18
− BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0, A1
Input-
Synchronous
Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 2M x 8 (four arrays each of 512K x 8) for CY7C1317AV18,
a single 1M x 18 array for CY7C1319AV18, and a single 512K x 36 array for CY7C1321AV18.
CY7C1317AV18 – Since the least two significant bits of the address internally are “00,” only 19
address inputs are needed to access the entire memory array.
CY7C1319AV18 – A0 and A1 are the inputs to the burst counter. These are incremented in a
linear fashion internally. 20 address inputs are needed to access the entire memory array.
CY7C1321AV18 – A0 and A1 are the inputs to the burst counter. These are incremented in a
linear fashion internally. 19 address inputs are needed to access the entire memory array.
All the address inputs are ignored when write access is deselected.
Pin Configurations (continued)
CY7C1321AV18 (512K × 36) – 11 × 15 FBGA
234
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
VSS/144M NC/36M
BWS2
K
R/W
BWS1
DQ27
DQ18
NC
NC
NC
TDO
NC
NC
DQ31
NC
NC
NC
TCK
NC
DQ28
A
BWS3
K
BWS0
VSS
AA0
A1
DQ19
VSS
VSS
VSS
VSS
VDD
A
VSS
VSS
VSS
VDD
DQ20
DQ21
VDDQ
DQ32
DQ23
DQ34
DQ25
DQ26
A
VDDQ
VSS
VDDQ
VDD
VDD
DQ22
VDDQ
VDD
VDDQ
VDD
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VSS
VSS
VSS
VSS
A
A
C
VSS
A
A
A
DQ29
VSS
NC
VSS
DQ30
NC
VREF
VSS
VDD
VSS
VSS
A
VSS
C
NC
DQ33
NC
DQ35
DQ24
VDD
A
89
10
11
DQ0
AVSS/72M
LD
CQ
A
NC
NC
DQ8
VSS
NC
DQ17
DQ7
NC
VSS
NC
DQ6
DQ14
NC
NC
VREF
NC
DQ3
VDDQ
NC
VDDQ
NC
DQ5
VDDQ
VDDQ
VDDQ
DQ4
VDDQ
NC
DQ13
NC
VDDQ
VDDQ
NC
VSS
NC
DQ1
NC
TDI
TMS
VSS
A
NC
A
DQ16
DQ15
NC
ZQ
DQ12
DQ2
DQ10
DQ11
DQ9
NC
A
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