CY7C1329
Document #: 38-05279 Rev. *B
Page 5 of 15
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby cur-
rent
ZZ > VDD − 0.2V
3
mA
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Cycle Descriptions [1,2,3]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
L
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
L
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
L
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
L
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
L
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
L
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
L
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
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