Real-Time Clocks

8

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Pin Description (continued)

PIN

24

28

NAME

FUNCTION

13

23

CS

Active-Low Chip-Select Input. This pin must be asserted low during a bus cycle for the device

to be accessed. CS must be kept in the active state during RD and WR. Bus cycles that take

place without asserting CS latch addresses, but no access occurs.

14

24

ALE

Address Latch Enable Input, Active High. This input pin is used to demultiplex the

address/data bus. The falling edge of ALE causes the address to be latched within the device.

15

25

WR

Active-Low Write Input. This pin defines the period during which data is written to the

addressed register.

17

27

RD

Active-Low Read Input. This pin identifies the period when the device drives the bus with read

data. It is an enable signal for the output buffers of the device.

18

28

KS

powered on in response to an active-low transition on the KS pin, as might be generated from

grounded and ABE set to 0.

19

1

IRQ

Active-Low Interrupt Request. This pin is an active-low output that can be used as an interrupt

input to a processor. The IRQ output remains low as long as the status bit causing the interrupt

is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the

application software must clear all enabled flag bits contributing to the pin’s active state. When

no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple

interrupting devices can be connected to an IRQ bus, provided that they are all open drain.

20

2

Connection for Primary Battery. This supply input is used to power the normal clock functions