ADG3242_06 datasheet(5/16 Pages) AD

Part #	ADG3242

Description	2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch

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ADG3242

Rev. A | Page 5 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

BE 1

A0 2

A1 3

GND 4

VCC

8

SEL

7

B0

6

B1

5

ADG3242

TOP VIEW

(Not to Scale)

ADI DIE MARK

A0

A1

B0

B1

GND

SEL VCC BE

ADG3242

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Figure 3. Die Pad Configuration (Die size: 550 μm × 820 μm)

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

BE

Bus Enable (Active Low).

2

A0

Port A0, Input or Output.

3

A1

Port A1, Input or Output.

4

GND

Ground (0 V) Reference.

5

B1

Port B1, Input or Output.

6

B0

Port B0, Input or Output.

7

SEL

Level Translation Select.

8

VCC

Positive Power Supply Voltage.

Table 4. Die Pad Coordinates (Measured from the Center of the Die)

Mnemonic

X(μm)

Y(μm)

BE

+93

+303

A0

+102

+150

A1

+168

−139

GND

+126

−266

B1

−88

−247

B0

−168

+121

SEL

−111

+279

VCC

−7

+303

Table 5. Truth Table

BE

SEL1

Function

L

A0 = B0, A1 = B1, 3.3 V to 1.8 V Level Shifting.

L

H

A0 = B0, A1 = B1, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting.

H

X

Disconnect.

1

SEL = 0 V only when VDD = 3.3 V ± 10%.

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