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CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Document Number: 38-05622 Rev. *C
Page 2 of 28
Logic Block Diagram (CY7C1317BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[7:0]
Output
Logic
Reg.
Reg.
Reg.
16
8
32
8
NWS[1:0]
VREF
16
C
C
8
LD
Control
Write
Reg
Write
Reg
Write
Reg
Write
Reg
CQ
CQ
19
R/W
DOFF
Logic Block Diagram (CY7C1917BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[8:0]
Output
Logic
Reg.
Reg.
Reg.
18
9
36
9
BWS[0]
VREF
18
C
C
9
LD
Control
Write
Reg
Write
Reg
Write
Reg
Write
Reg
CQ
CQ
19
R/W
DOFF