CY7C1378C-166AXI datasheet(10/13 Pages) CYPRESS

Part #	CY7C1378C-166AXI

Description	9-Mbit (256K x 32) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 13 page

CY7C1378C

Document #: 38-05687 Rev. *F

Page 10 of 13

Switching Waveforms

Read/Write Timing[17, 18, 19]

Notes:

17. For this waveform ZZ is tied LOW.

18. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

19. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

WRITE

D(A1)

123

456789

CLK

t CYC

tCL

tCH

10

CE

tCEH

tCES

WE

CEN

tCENH

tCENS

BW[A:D]

ADV/LD

tAH

tAS

ADDRESS

A1

A2

A3

A4

A5

A6

A7

tDH

tDS

Data

In-Out (DQ)

tCLZ

D(A1)

D(A2)

D(A5)

Q(A4)

Q(A3)

D(A2+1)

tDOH

tCHZ

tCO

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE

tOEV

tOELZ

tOEHZ

tDOH

DON’T CARE

UNDEFINED

Q(A6)

Q(A4+1)

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