8 / 35 page  CY7C1381CV25 CY7C1383CV25 Document #: 38-05241 Rev. *B Page 8 of 35 VDDQ 4,11,20,27, 54,61,70,77 A1,F1,J1,M1,U1 , A7,F7,J7,M7,U7 C3,C9,D3, D9,E3,E9, F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 I/O Power Supply Power supply for the I/O circuitry. VSS 17,40,67,90 H2,D3,E3,F3,H3 ,K3, M3,N3, P3,D5,E5,F5,H5 ,K5, M5,N5,P5 C4,C5,C6, C7,C8,D5, D6,D7,E5, E6,E7,F5, F6,F7,G5, G6,G7,H5, H6,H7,J5, J6,J7,K5,K6,K7, L5,L6,L7,M5,M6 ,M7,N4,N8 Ground Ground for the core of the device. VSSQ 5,10,21,26, 55,60,71,76 - - I/O Ground Ground for the I/O circuitry. TDO - U5 P7 JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. TDI - U3 P5 JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS - U2 R5 JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be discon- nected or connected to VDD. This pin is not available on TQFP packages. TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC 16,38,39,66 B1,C1,R1,T1,T2 ,J3,D4,L4,J5,R5 ,T6,U6,B7,C7,R 7 A1,A11,B1, B11,C2,C10,H1, H3,H9, H10,N2,N5,N7, N10,P1,P2,R2 - No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M and 288M are address expansion pins are not internally connected to the die. VSS/DNU 14 - - Ground/DNU This pin can be connected to Ground or should be left floating. CY7C1381CV25–Pin Definitions (continued) Name TQFP (3-Chip Enable) BGA (1-Chip Enable) fBGA (3-Chip Enable) I/O Description |
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