18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381CV25
CY7C1383CV25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05241 Rev. *B
Revised April 19, 2004
Features
• Supports 133-MHz bus operations
• 512K X 36/1M X 18 common I/O
• 2.5V +/–5% core power supply (VDD)
• 2.5V I/O supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.5 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP,119-ball BGA
and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36
and 1M x 18 Synchronous Flow through SRAMs, respectively
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1381CV25/CY7C1383CV25 allows either inter-
leaved or linear burst sequences, selected by the MODE input
pin. A HIGH selects an interleaved burst sequence, while a
LOW selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1381CV25/CY7C1383CV25 operates from a +2.5V
core power supply. All outputs also operate with a +2.5 supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
117 MHz
100 MHz
Unit
Maximum Access Time
6.5
7.5
8.5
ns
Maximum Operating Current
210
190
175
mA
Maximum CMOS Standby Current
70
70
70
mA
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
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