4 / 10 page
CY7C1399B
Document #: 38-05071 Rev. *D
Page 4 of 10
Switching Characteristics Over the Operating Range[6]
1399B-10
1399B-12
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
10
12
ns
tOHA
Data Hold from Address Change
3
3
ns
tACE
CE LOW to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
5
ns
tLZOE
OE LOW to Low Z[7]
00
ns
tHZOE
OE HIGH to High Z[7, 8]
55
ns
tLZCE
CE LOW to Low Z[7]
33
ns
tHZCE
CE HIGH to High Z[7, 8]
56
ns
tPU
CE LOW to Power-Up
0
0
ns
tPD
CE HIGH to Power-Down
10
12
ns
Write Cycle[9, 10]
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
8
8
ns
tAW
Address Set-Up to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-Up to Write End
5
7
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High Z[9]
77
ns
tLZWE
WE HIGH to Low Z[7]
33
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and capacitance CL = 30 pF.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
