CY7C1441AV25
CY7C1443AV25
CY7C1447AV25
Document #: 38-05349 Rev. *F
Page 8 of 31
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The
CY7C1441AV25/CY7C1443AV25/CY7C1447AV25
supports secondary cache in systems utilizing either a linear
or interleaved burst sequence. The interleaved burst order
supports Pentium and i486 processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is deter-
mined by sampling the MODE input. Accesses can be initiated
with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active (see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise, the appropriate data will be latched and
written into the device. Byte writes are allowed. All I/Os are
tri-stated during a byte write. Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
DQPX
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical
to DQs. During write sequences, DQPx is controlled by BWX correspondingly.
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation. Mode Pin has an internal
pull-up.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power Supply
Power supply for the I/O circuitry.
VSS
Ground
Ground for the core of the device.
VSSQ
I/O Ground
Ground for the I/O circuitry.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP packages.
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin can be left floating or connected to
VDD through a pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
TCK
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized,
this pin must be connected to VSS. This pin is not available on TQFP
packages.
NC
–
No Connects. Not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M, NC/1G are address expansion pins are not internally
connected to the die.
Pin Definitions (continued)
Name
I/O
Description
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