CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Document #: 38-06029 Rev. *C
Page 9 of 20
AC Test Loads and Waveforms[9, 10]
3.0V
3.3V
OUTPUT
R1 = 330
Ω
R2 = 510
Ω
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3 ns
OUTPUT
Vth = 2.0V
Equivalent to:
THÉVENIN EQUIVALENT
Rth = 200
Ω
ALL INPUT PULSES
≤ 3 ns
Switching Characteristics Over the Operating Range
Parameter
Description
7C42X5V-15
7C42X5V-25
7C42X5V-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tS
Clock Cycle Frequency
66.7
40
28.6
MHz
tA
Data Access Time
2
11
2
15
2
20
ns
tCLK
Clock Cycle Time
15
25
35
ns
tCLKH
Clock HIGH Time
6
10
14
ns
tCLKL
Clock LOW Time.
6
10
14
ns
tDS
Data Set-up Time
4
6
7
ns
tDH
Data Hold Time
1
2
2
ns
tENS
Enable Set-up Time
4
6
7
ns
tENH
Enable Hold Time
1
2
2
ns
tRS
Reset Pulse Width[11]
15
25
35
ns
tRSR
Reset Recovery Time
10
15
20
ns
tRSF
Reset to Flag and Output Time
18
25
35
ns
tPRT
Retransmit Pulse Width
15
25
35
ns
tRTR
Retransmit Recovery Time
15
25
35
ns
tOLZ
Output Enable to Output in Low Z[12]
0
0
0
ns
tOE
Output Enable to Output Valid
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[12]
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
11
15
20
ns
tREF
Read Clock to Empty Flag
11
15
20
ns
tPAFasynch
Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
18
22
25
ns
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
11
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
18
22
25
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
11
15
20
ns
tHF
Clock to Half-Full Flag
16
20
25
ns
Notes:
9. CL = 30 pF for all AC parameters except for tOHZ.
10. CL = 5 pF for tOHZ.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
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