CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document #: 38-06012 Rev. *A
Page 6 of 20
tOHZ
Output Enable to Output in High Z[12]
3
7
3
8
3
12
ns
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAFasynch
Clock to Programmable Almost-Full
Flag[13] (Asynchronous mode,
VCC/SMODE tied to VCC)
15
16
20
ns
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to
VSS)
8
10
15
ns
tPAEasynch
Clock to Programmable Almost-Empty
Flag[13] (Asynchronous mode, VCC/SMODE
tied to VCC)
15
16
20
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to
VSS)
8
10
15
ns
tHF
Clock to Half-Full Flag
12
16
20
ns
tXO
Clock to Expansion Out
6
10
15
ns
tXI
Expansion in Pulse Width
4.5
6.5
10
ns
tXIS
Expansion in Set-Up Time
4
5
10
ns
tSKEW1
Skew Time between Read Clock and
Write Clock for Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and
Write Clock for Empty Flag
5
6
10
ns
tSKEW3
Skew Time between Read Clock and
Write Clock for Programmable Almost
Empty and Programmable Almost Full
Flags (Synchronous Mode only)
10
15
18
ns
Note:
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Switching Characteristics Over the Operating Range (continued)
7C4255/65/75/85V
-10
7C4255/65/75/85V
-15
7C4255/65/75/85V
-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
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