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CY7C4282V
CY7C4292V
Document #: 38-06014 Rev. *B
Page 6 of 15
Depth Expansion Configuration
The CY7C4282V/92V can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282V/92Vs.
Maximum depth is limited only by signal loading. Follow these
steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device.
4. EF and FF composite flags are created by ORing together
each individual respective flag.
Figure 3. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
WRITECLOCK (WCLK)
WRITEENABLE (WEN)
RESET (RS)
FF
FF
EF
EF
XI
FIRST LOAD (FL)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUTENABLE (OE)
XO
FF
EF
XI
XO
VCC
FL
FF
EF
XI
XO
7C4282V
7C4292V
VCC
FL
DATA IN (D)
DATA OUT (Q)
WCLK
WEN
RS
RCLK
REN
OE
DQ
7C4282V
7C4292V
WCLK
WEN
RS
RCLK
REN
OE
DQ
WCLK
WEN
RS
D
RCLK
REN
OE
Q
FL
7C4282V
7C4292V
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