16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06013 Rev. *B
Revised August 2, 2005
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261V)
• 32K × 9 (CY7C4271V)
• 64K × 9 (CY7C4281V)
• 128K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
•Low power
—ICC = 25 mA
—ISB = 4 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and programmable Almost Empty and
Almost Full status flags
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width- Expansion capability
• Pin-compatible 3.3V solutions for CY7C4261/71/81/91
• Pin-compatible density upgrade to CY7C42X1V family
• Pb-Free Packages Available
Functional Description
The CY7C4261/71/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71/81/91V are pin-compatible to the
CY7C42x1V Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1 and WEN2/LD are held active, data is continually
written into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read enable pins (REN1, REN2). In addition,
the CY7C4261/71/81/91V has an output enable pin (OE). The
read (RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
LogicBlock Diagram
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0–8
RCLK
Q0–8
WEN1
WCLK
RS
OE
Dual Port
WEN2/LD
REN1 REN2
EF
PAE
PAF
FF
RAM Array
16K/32K
x 9
64K/128K
PLCC
D1
D0
RCLK
VCC
GND
WCLK
WEN2/LD
Q8
Q7
PAF
PAE
5
6
7
8
9
10
11
12
13
REN1
OE
REN2
4321
31 30
32
21
22
23
24
27
28
29
25
26
14 15 16 17 18 19 20
Q6
Q5
WEN1
RS
Top View
CY7C4261V
CY7C4271V
Pin Configuration
CY7C4281V
CY7C4291V
CY7C4281V/CY7C4291V CY7C4261V/CY7C4271V16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs
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